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TRR404 - Next Generation Electronics With Active Devices in Three Dimensions
In the last years the actual size of a transistor did not significantly scale any further and the doubling of the number of devices on an integrated circuit in a new technology node as described by Moore’s Law has been achieved instead by eliminating dead space in a technology/circuit codesign approach. While this approach is still successful, it does not deliver the same benefits as Dennard’s scaling and will come to an end soon. Monolithic stacking of multiple transistors on top of each other is the next logical step. At the same time, in heterogeneous system integration, several chips are combined in one package to realize a system complexity beyond what is possible with most advanced technology in a cost-efficient way. In this Collaborative Research Center (TRR) we will look into the future by exploring the possibilities of placing active devices in the entire three-dimensional structure of the chip. We aim at exploring the possibilities to integrate different logic and memory functions into the Back-End of Line and by this achieving much higher integration density on the same real estate.
Field of action:
CMOS and more
- Faculty 6 – Electrical Engineering and Information Technology
Address:
Lehrstuhl für Höchstfrequenzelektronik (HFE)
Contact:
Univ.-Prof. Dr. Renato Negra
Renato.negra@hfe.rwth-aachen.de
Homepage:
http://www.hfe.rwth-aachen.de
Status:
in preparation